Company : POWERWAVE
Job Location : Hyderabad
Job Description : Powerwave Technologies R&D India Pvt Ltd.,
Engineer - FPGA
Job Description :
We are inviting Walk-in interviews for FPGA team based on the below requirement.
If you would like appear for the interview, please send your profile with available Date & Time (24th to 26th) to below email ID at the earliest for screening:
sudheer.kumar(at)pwav.com
Qualification: B.Tech / M.Tech( Electronics, Communications (2010 / 2011))
Eligibility Criteria: 60% Aggregate
Experience: 0+ Years
Skills: VHDL / Verilog; Digital Electronics (Basics, State Machine Design, FPGA basics); Engineering Mathematics
Desired Profile :
Education: B.Tech / M.Tech in Electronics, Communications with 60% Marks
Freshers : 2010 / 2011 passed out
Experience: 0+
If Experienced: FPGA architechure, RTL, VHDL, Verilog, Digital Signal Processing, MATLAB, Xilinx, Filter Design.
Knowledge, Skills and Abilities:
* Effective verbal and written communication skills that clearly convey information and ideas. Ability to communicate to individuals or groups through a variety of media in a manner that engages the audience and helps them understands the information.
* Ability to use Word, Excel, Microsoft Project and Visio software programs, to a level of professional proficiency. Able to produce professional Engineering reports including introductions, conclusions and recommendations.
* Ability to analyze and resolve technical problems of a moderate complexity quickly and independently
* Working knowledge of programming languages including C/C++, Visual Basic and structured programming techniques and/or knowledge of FPGA programming language, techniques and tools.
* Basic knowledge of electronic design.
* Knowledge of simulators, ICE debuggers and Integrated Development Environments and/or FPGA simulators and functions.
* Competent RF and/or Digital lab skills
* Ability to self-manage technical design activities from concept to validation including and test plan and methodology.
* Working knowledge of communication theory.
* Ability to use MATLAB, Quartus – II/ Xilinx ISE, Timing Analyzer tools.
* Ability to code using VHDL/Verilog.
* Ability to apply Engineering Mathematics concepts (Linear Algebra, Probability.)
* Knowledge of high end FPGA architectures
Selection Procedure: Written Test followed by Technical and HR in-person interview.
Interview Dates: 24th to 26th January, 2011. Time: 9:30 AM – 5:30 PM
Venue:
Technologies R & D India Pvt. Ltd.
4th floor, B-Block, Cyber pearl
Ascendas IT Park |
Madhapur
Hyderabad- 500 081
Ph: 040 - 40351111
If you would like appear for the interview, please send your profile with available Date & Time (24th to 26th) to below email ID at the earliest for screening:
sudheer.kumar(at)pwav.com
